Detailed Specifications of the "Cascade Lake SP" Intel Xeon Processor Scalable Family CPUs

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Detailed Specifications of the “Cascade Lake SP” Intel Xeon Processor Scalable Family CPUs

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This article provides in-depth discussion and analysis of the 14nm Intel Xeon Processor Scalable Family (formerly codenamed "Cascade Lake-SP" or "Cascade Lake Scalable Processor"). "Cascade Lake-SP" processors replace the previous 14nm "Skylake-SP" microarchitecture and are available for sale as of April 2, 2019. On February 24, 2020, a set of "Cascade Lake Refresh" Xeon models were released with increased clock speeds and improved cost/performance. These Xeon CPUs have been superseded by the <a href="https://www.microway.com/knowledge-center-articles/detailed-specifications-of-the-ice-lake-sp-intel-xeon-processor-scalable-family-cpus/" rel="noopener noreferrer" target="_blank">3rd-generation Intel Xeon 'Ice Lake SP' scalable processors</a>.

These new CPUs are the second iteration of Intel's Xeon Processor Scalable Family. They remain compatible with the existing workstation and server platforms, but bring incremental performance along with additional capabilities and options.

<h2>Important features/changes in Xeon Scalable Processor Family "Cascade Lake SP" CPUs include:</h2>
<ul>
	<li>Up to 28 processor cores per socket (with options for 4-, 6-, 8-, 10-, 12-, 16-, 18-, 20-, 24-, and 26-cores)</li>
	<li>Improved CPU clock speeds (with Turbo Boost up to 4.4GHz)</li>
	<li>Continued high performance with the AVX-512 instruction capabilities of the previous generation:
<ul>
	<li>AVX-512 instructions (up to 16 double-precision FLOPS per cycle per AVX-512 FMA unit)</li>
	<li>Up to two AVX-512 FMA units per CPU core (depends upon CPU SKU)</li>
</ul>
</li>
	<li>Introduction of new AVX-512 VNNI instruction:
<ul>
	<li>Intel Deep Learning Boost (VNNI) provides significant, more efficient deep learning inference acceleration</li>
	<li>Combines three AVX-512 instructions (VPMADDUBSW, VPMADDWD, VPADDD) into a single VPDPBUSD operation</li>
</ul>
</li>
	<li>Memory capacity &amp; performance features:
<ul>
	<li>Six-channel memory controller on each CPU</li>
	<li>Support for DDR4 memory speeds up to 2933MHz (up from 2666MHz)</li>
	<li>Large-memory capabilities with Intel Optane DC Persistent Memory</li>
	<li>All CPU models support up to 1TB-per-socket system memory</li>
	<li>Optional CPUs support up to 4.5TB-per-socket system memory (only available on certain SKUs)</li>
</ul>
</li>
	<li>Introduction of Intel Speed Select processor models:
<ul>
	<li>Certain processors support three distinct operating points</li>
	<li>Each operating point provides a different number of CPU cores</li>
	<li>CPU clock and Turbo Boost speeds optimized for each core count</li>
</ul>
</li>
	<li>Integrated hardware-based security mitigations against side-channel attacks</li>
</ul>
With a product this complex, it’s very difficult to cover every aspect of the design. Here, we concentrate primarily on the performance of the processors for HPC &amp; AI applications.

<a name="specialization"></a>
<h1>Specialization of Intel Xeon CPUs</h1>
The new "Cascade Lake-SP" processors will be be familiar to existing users. Just as in the previous generation, the processor family is divided into four tiers: Bronze, Silver, Gold, and Platinum. Bronze provides modest performance for a low price. The Silver and Gold models are in the price/performance range familiar to HPC users/architects. Platinum models are in a higher price range than HPC groups are typically accustomed to (Platinum tier targets Enterprise workloads, and is priced accordingly).

However, this new generation is not simply a revision of the previous models. Increasingly, we are seeing processors that have been designed with a particular workload in mind. The "Cascade Lake SP" Xeons introduce several new specialized CPU models:
<ul>
	<li>S: search optimized</li>
	<li>N: network function virtualization (NFV) optimized</li>
	<li>V: virtualization density optimized</li>
	<li>Y: Intel speed select</li>
	<li>U: single-socket optimized</li>
</ul>
In the case of the first two specializations (search and NFV), specific CPU clock frequencies and Turbo Boost speeds are guaranteed only for those specific workloads. Running other workloads on these optimized CPUs will likely lead to CPU throttling, which would be undesirable. The virtualization density optimized models provide high CPU core counts within relatively modest power envelopes. However, the processor clock and memory clock frequencies are reduced to accomplish this. Considering these limitations, the search-, NFV-, and virtualization-optimized models will not be included in our review

The single-socket optimized CPUs are indicated with a U suffix in the model name (e.g., Xeon 6210U). These CPUs are quite cost-effective for what they offer (a 6200-series CPU for a 5200-series price). However, they do not include UPI links and thus can only be installed in systems with a single processor.

Intel Speed Select CPUs are indicated with a Y suffix in the model name (e.g., Xeon 6240Y). Each of these three CPUs offers the same core count and clock speed as their non-Y counterpart. However, the system can be rebooted into a lower core-count mode which boosts the CPU clock and Turbo Boost speeds. The Speed Select models available in this generation are: 8260Y, 6240Y, and 4214Y. Although these models are not called out by name below, understand that alternate versions of Xeon 8260, 6240, and 4214 are available if you need core count &amp; clock speed flexibility.

Before diving into the details, it helps to keep in mind the following recommendations. Based on our experience with HPC and Deep Learning deployments, our guidance for selecting Xeon tiers is as follows:
<ul>
	<li>Intel Xeon Bronze - not recommended for HPC Base-level model with low performance.</li>
	<li>Intel Xeon Silver - suitable for entry-level HPC 4200-series models offer slightly improved performance over previous generations.</li>
	<li>Intel Xeon Gold - recommended for most HPC workloads The best balance of performance and price. In particular, the 6200-series models should be preferred over the 5200-series models, because they have twice the number of AVX-512 units</li>
	<li>Intel Xeon Platinum - recommended only for specific HPC workloads Although these 8200-series models provide the highest performance, their higher price makes them suitable only for particular workloads which require their specific capabilities (e.g., high core count, large SMP, and large-memory Compute Nodes).</li>
</ul>
* Given their positioning, the Intel Xeon Bronze products will not be included in our review

<a name="performance"></a>
<h1>Exceptional Computational Performance</h1>
The Xeon "Cascade Lake SP" processors deliver new capabilities and unprecedented performance. Most models provide over 1 TFLOPS (one teraflop of double-precision 64-bit performance per second) and a couple models provide 2 TFLOPS. This performance is achieved with high core counts and AVX-512 instructions with FMA (just as in the previous generation). The plots in the tabs below compare the performance ranges for these new CPUs:
[tabby title="AVX-512 Instructions"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_Theoretical_Peak_Performance_AVX-512.png" alt="Comparison chart of Intel Xeon Cascade Lake SP CPU theoretical GFLOPS performance with AVX-512 instructions" width="750" height="660" class="aligncenter size-full wp-image-11259" />

[tabby title="AVX2 Instructions"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_Theoretical_Peak_Performance_AVX2.png" alt="Comparison chart of Intel Xeon Cascade Lake SP CPU theoretical GFLOPS performance with AVX2 instructions" width="750" height="660" class="aligncenter size-full wp-image-11264" />

[tabbyending]
As shown above, the shaded/colored bars indicate the expected performance ranges for each CPU model. The first plot shows performance when using Intel's AVX-512 instructions with FMA. Note that only a small set of codes will be capable of issuing exclusively AVX-512 FMA instructions (e.g., LINPACK). Most applications issue a variety of instructions and will achieve lower than peak FLOPS. Applications which have not been re-compiled with an appropriate compiler will not include AVX-512 instructions and thus achieve lower performance. Those expected performance ranges are shown in the plot of AVX2 Instruction performance.

Although the ordering of the above plots may seem arbitrary, they are sorted by price (as discussed in the next section). The lowest-performance models provide fewer numbers of CPU cores and fewer AVX math units. Higher-end models provide a mix of higher core counts and higher clock speeds. A few CPU models, such as Xeon 6244 and Xeon 8256, strongly favor high clock speeds over CPU core count (which results in lower overall FLOPS throughput). HPC and AI groups are expected to favor the Intel Xeon Gold processor models.

<a name="prices"></a>
<h1>Intel Xeon "Cascade Lake SP" Price Ranges</h1>
The pricing of the Xeon Processor Scalable Family spans a wide range, so budget must be kept at top of mind when selecting options. It would be frustrating to plan for 28-core processors when the budget cannot support a price of more than $10,000 per CPU. The plot below compares the prices of the Xeon "Cascade Lake SP" processors:

As in the above plot, all the CPUs in this article are sorted by price. Most HPC users are expected to select CPU models from the Gold Xeon 6200-series. These models provide close to peak performance for a price under $4,000 per processor. Certain specialized applications will leverage the Platinum Xeon 8200-series, such as very large memory nodes (>3TB system memory).

To ease comparisons, all of the plots in this article are ordered to match the above plot. Keep this pricing in mind as you review this article and plan your system architecture.

<a name="specifications"></a>
<h1>Intel "Cascade Lake SP" Xeon Processor Scalable Family Specifications</h1>
The sets of tabs below compare the features and specifications of this new Xeon processor family. As you will see, the Silver (4200-series) and lower-end Gold (5200-series) CPU models offer fewer capabilities and lower performance. The higher-end Gold (6200-series) and Platinum (8200-series) offer more capabilities and higher performance. Additionally, certain CPU SKUs have special models integrating additional specializations:
<ul>
	<li>Enabled for Intel Speed Select (indicated with a Y suffix on the part number)</li>
	<li>Support for up to 4.5TB of memory per CPU socket (indicated with an L suffix on the part number)
	(these same CPUs have a lower-cost alternate SKU supporting 2TB memory per socket (indicated with an M suffix on the part number)
</li>
	<li>Designed for single CPU socket systems (indicated with a U suffix on the part number)</li>
	<li>All Gold- and Platinum-series CPUs support Intel's new Optane DC Persistent Memory</li>
</ul>

[tabby title="CPU Cores"]
Most HPC groups will find that processors with 12 to 20 CPU cores fit within their budget. Systems with up to 24-cores per CPU will not be shockingly expensive. However, the 26-core and 28-core models are only available within the Platinum tier and will be at a higher cost than most groups would consider cost-effective.
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_Number_of_Cores.png" alt="Comparison chart of Intel Xeon Cascade Lake SP CPU core counts and capabilities" width="750" height="720" class="aligncenter size-full wp-image-11269" />

[tabby title="CPU Speed"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_Base_Clock_Speeds.png" alt="Comparison chart of Intel Xeon Cascade Lake SP processor clock speeds" width="750" height="660" class="aligncenter size-full wp-image-11344" />

[tabby title="Memory Speed"]
Memory performance of Intel Xeon "Cascade Lake-SP" is fairly straightforward, with the Silver CPUs providing a lower speed than the Gold and Platinum models. The amount of memory bandwidth available per CPU core is an important factor, but is simply a function of the number of cores. Users planning to run on CPUs with higher core counts need to ensure that each core won’t be starved of data.

It is important to note that some system platforms support two memory slots per memory channel (a total of 24 DIMMs in a dual-socket system). If both memory slots are populated with memory, the slots will run no faster than 2666MHz (this is simply an electrical/signaling limit).
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_Memory_Performance.png" alt="Comparison chart of Intel Xeon Cascade Lake SP memory performance" width="750" height="660" class="aligncenter size-full wp-image-11270" />

[tabby title="AVX Units"]
As shown, the 6200-series and 8200-series CPUs provide two AVX-512 units per processor core. All remaining CPUs (with the exception of the Xeon 5222) include a single AVX-512 unit.
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_Number_of_AVX-512_Units.png" alt="Comparison chart of Intel Xeon Cascade Lake SP CPU number of AVX-512 math units" width="750" height="660" class="aligncenter size-full wp-image-11276" />

[tabby title="L3 Cache"]
The "Cascade Lake-SP" CPUs have been designed to offer at least 1.375MB of L3 cache per processor core. As shown below, there are several models which feature a larger quantity of L3 per core. Remember that each core also has 1MB of private L2 cache. In this architecture, the L3 cache is designed as a fallback for data that spills out of L2.
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_L3_Cache_Size.png" alt="Comparison chart of Intel Xeon Cascade Lake SP L3 cache size" width="750" height="660" class="aligncenter size-full wp-image-11272" />

[tabby title="UPI"]
The UPI capabilities of these CPUs are nearly identical to the previous generation. Each CPU supports two or three UPI links operating at 9.6GT/s to 10.4GT/s. Only the Xeon 6200-series and 8200-series support the higher number of UPI links, which allows greater connectivity between sockets. Dual-socket systems are the most popular configuration for HPC, but not all dual-socket platforms support all three UPI links - review your proposed system architecture.
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_UPI_Performance.png" alt="Comparison chart of Intel Xeon Cascade Lake SP UPI performance" width="750" height="660" class="aligncenter size-full wp-image-11273" />

[tabby title="Socket Count"]
Although dual-socket systems are the most common for HPC &amp; AI workloads, there are use cases requiring larger or smaller numbers of CPUs. The plot below compares the various CPU socket counts supported by this processor line-up (ranging from a single socket to eight sockets). Take note that although the 5200-series CPUs support four sockets, they only provide dual UPI links. HPC users are advised to look to 6200- and 8200-series models for four-socket systems.
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_Supported_Socket_Count.png" alt="Comparison chart of Intel Xeon Cascade Lake SP CPU supported socket counts" width="750" height="660" class="aligncenter size-full wp-image-11277" />

[tabby title="TDP"]
Although there are still processor models in the same power range as previous generations, an increasing number of models feature TDPs above 140 Watts. A few models even reach over 200 Watts. HPC users must be certain that the systems they select have received thorough thermal validation. Systems which run warm will suffer lower performance. In particular, care is recommended with higher clock speed CPUs (2.5+ GHz) which may reduce their clock speeds more aggressively to remain within thermal limits.
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_TDP_Wattage.png" alt="Comparison chart of Intel Xeon Cascade Lake SP TDP power requirements" width="750" height="660" class="aligncenter size-full wp-image-11274" />

[tabbyending]

In addition to the specifications called out above, technical readers should note that the "Cascade Lake SP" CPU architecture inherits most of the architectural design of the previous "Skylake-SP" architecture, including the mesh processor layout, redesigned L2/L3 caches, greater UPI connectivity between CPU sockets, and improvements to the processor frequency speeds/turbo. A more comprehensive list of features is shown at the end of the article.

<a name="clockspeeds"></a>
<h1>Clock Speeds &amp; Turbo Boost</h1>
Just as in the previous generation, the "Cascade Lake-SP" architecture acknowledges that highly-parallel/vectorized applications place the highest load on the processor cores (requiring more power and generating more heat). While a CPU core is executing intensive vector tasks (AVX2 or AVX-512 instructions), the clock speed will be adjusted downwards to keep the processor within its power limits (TDP).

In effect, this will result in the processor running at a lower frequency than the standard clock speed advertised for each model. For that reason, each processor is assigned three frequency ranges:
<ul>
	<li>AVX-512 mode: due to the high requirements of AVX-512/FMA instructions, clock speeds will be lowered while executing AVX-512 instructions *</li>
	<li>AVX2 mode: due to the higher requirements of AVX2/FMA instructions, clock speeds will be somewhat lower while executing AVX instructions *</li>
	<li>Non-AVX mode: while not executing "heavy" AVX instructions, the processor will operate at the "stock" frequency</li>
</ul>
Each of the "modes" above is actually a range of CPU clock speeds. The CPU will run at the highest speed possible for the particular set of CPU instructions that have been issued. It is worth noting that these modes are isolated to each core. Within a given CPU, some cores may be operating in AVX mode while others are operating in Non-AVX mode.

* Intel has applied a 1-millisecond hysteresis window on each CPU core to prevent rapid frequency transitions

<h2>AVX-512, AVX, and Non-AVX Turbo Boost in Xeon "Cascade Lake-SP" Scalable Family processors</h2>
Each CPU also includes the Turbo Boost feature which allows each processor core to operate well above the "base" clock speed during most operations. The precise clock speed increase depends upon the number &amp; intensity of tasks running on each CPU. However, Turbo Boost speed increases also depend upon the types of instructions (AVX-512, AVX, Non-AVX).

The plots below demonstrate processor clock speeds under the following conditions:
<ul>
	<li>All cores on the CPU actively running Non-AVX, AVX, or AVX-512 instructions</li>
	<li>A single active core running Non-AVX, AVX, or AVX-512 instructions (all other cores on the CPU must be idle)</li>
</ul>
The dotted lines represent the range of clock speeds for Non-AVX instructions. The thin grey bars represent the range of clock speeds for AVX2/FMA instructions. The thicker shaded/colored bars represent the range of clock speeds for AVX-512/FMA instructions.

[tabby title="All CPU cores active"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_Frequency_Speeds_AVX-512_and_AVX2_Instructions_All-Core.png" alt="Comparison chart of Intel Xeon Cascade Lake SP CPU clock speeds with all cores active" width="750" height="660" class="aligncenter size-full wp-image-11281" />

[tabby title="A single CPU core active"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_CPU_Frequency_Speeds_AVX-512_and_AVX2_Instructions_Single-Core.png" alt="Comparison chart of Intel Xeon Cascade Lake SP CPU clock speeds with only one core active" width="750" height="660" class="aligncenter size-full wp-image-11282" />

[tabbyending]

Note that despite the clear rules stated above, each Turbo Boost value is still a range of clock speeds. Because workloads are so diverse, Intel is unable to guarantee one specific clock speed for AVX-512, AVX, or Non-AVX instructions. Users are guaranteed that cores will run within a specific range, but each application will have to be benchmarked to determine which frequencies a CPU will operate at.

Despite the perceived reduction in performance when running these vector instructions, keep in mind that AVX-512 roughly doubles the number of operations which can be completed per cycle. Although the clock speeds might be reduced by nearly 1GHz, the overall throughput is increased. HPC users should expect their processors to be running in AVX or AVX-512 mode most of the time.

<a name="cost-effectiveness-and-efficiency"></a>
<h1>Cost-Effectiveness and Power Efficiency of Xeon "Cascade Lake SP" CPUs</h1>
Many of these new processors have the same price structure as earlier Xeon server CPU families. However, the prices and power requirements for some of the premium models are fairly high. Savvy readers may find the following facts useful:
<ul>
	<li>HPC applications run best on the higher-end Gold and Platinum CPU models (6200- and 8200-series), as all of the lower-end CPUs provide only half the number of math units.</li>
	<li>Applications which can be satisfied by a single CPU will benefit greatly from the single-socket Xeon 62xxU models</li>
	<li>The Platinum models (8200-series) are generally targeted towards Enterprise and Finance - these carry higher prices than other models.</li>
</ul>

The plots below compare the cost-effectiveness and power efficiency of these CPU models. The intent is to go beyond the raw "speeds and feeds" of the processors to determine which models will be most attractive for HPC and Deep Learning/AI deployments.

[tabby title="Cost-Effectiveness for HPC &amp; AI"]
In general, the Xeon 6200-series provide the most cost-effective performance. The Xeon 4200- and 5200-series CPUs are priced lower, but include only a single AVX-512 math unit (which reduces their cost effectiveness considerably).

The Xeon 8256 is an outlier as it was not designed for cost-effectiveness (instead optimizing for four high-speed CPU cores).

[tabby title="CPU Power Efficiency"]
This plot compares the power requirements (TDP) versus performance throughput of each CPU. Although this generation includes some of the highest-wattage CPUs to date, each is actually quite power efficient. In fact, even the 205-Watt CPU models are among the top most-efficient models in this product line. Overall, any CPU selected from the Xeon 6200- or 8200-series will be close to the most efficient CPU on the market. Groups which select the lower-price 4200-series CPUs will end up spending more on power per useful work completed.

[tabbyending]

<a name="recommended-cpus"></a>
<h1>Recommended CPU Models for HPC &amp; AI/Deep Learning</h1>
Although many of these CPU models will offer excellent performance, it is common for HPC sites to set a floor on CPU clock speeds (usually around 2.5GHz). The intent is to ensure that no workload suffers too low of a performance. While there are users who would prefer higher clock speeds, experience shows that most groups settle on a value of 2.5GHz to 2.6GHz. With that in mind, the comparisons below highlight only those CPU models which offer 2.5+GHz performance.
[tabby title="2.5+GHz Core Counts"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_2.5Ghz_CPU_Number_of_Cores.png" alt="Comparison chart of Intel Xeon Cascade Lake SP 2.5+GHz CPU core counts" width="750" height="720" class="aligncenter size-full wp-image-11299" />

[tabby title="AVX-512 Performance"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_2.5GHz_Theoretical_Peak_Performance_AVX-512.png" alt="Comparison chart of Intel Xeon Cascade Lake SP 2.5+GHz CPU throughput with AVX-512 instructions" width="750" height="660" class="aligncenter size-full wp-image-11300" />

[tabby title="AVX2 Performance"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_2.5GHz_Theoretical_Peak_Performance_AVX2.png" alt="Comparison chart of Intel Xeon Cascade Lake SP 2.5+GHz CPU throughput with AVX2 instructions" width="750" height="660" class="aligncenter size-full wp-image-11301" />

[tabby title="2.5+GHz Cost-Effectiveness"]
<img src="https://www.microway.com/wp-content/uploads/Xeon_Cascade-Lake-SP_2.5GHz_Cost-Effectiveness.png" alt="Comparison chart of Intel Xeon Cascade Lake SP 2.5+GHz CPU cost effectiveness" width="750" height="660" class="aligncenter size-full wp-image-11302" />

[tabbyending]

<a name="summary-of-features"></a>
<h1>Summary of features in Xeon Scalable Family "Cascade Lake-SP" processors</h1>
In addition to the capabilities mentioned at the top of this article, these processors include many of the successful features from earlier Xeon designs. They also include lower-level changes that may of interest to expert users. The list below provides a more detailed summary of relevant technology features in Cascade Lake-SP:
<ul>
 <li>Up to 28 processor cores per socket (with options for 4-, 6-, 8-, 10-, 12-, 16-, 18-, 20-, 24-, and 26-cores)</li>
 <li>Improved CPU clock speeds (with Turbo Boost up to 4.4GHz)</li>
 <li>Continued high performance with the AVX-512 instruction capabilities of the previous generation:
<ul>
 <li>AVX-512 instructions (up to 16 double-precision FLOPS per cycle per AVX-512 FMA unit)</li>
 <li>Up to two AVX-512 FMA units per CPU core (depends upon CPU SKU)</li>
</ul>
</li>
 <li>Introduction of new AVX-512 VNNI instruction:
<ul>
 <li>Intel Deep Learning Boost - the new 8-bit Vector Neural Network Instruction (VNNI) provides significant, more efficient deep learning inference acceleration</li>
 <li>Combines three AVX-512 instructions (VPMADDUBSW, VPMADDWD, VPADDD) into a single VPDPBUSD operation</li>
</ul>
</li>
 <li>As introduced with "Haswell" and "Broadwell", these CPUs continue to support 128-bit AVX and 256-bit AVX2 Advanced Vector Extensions with FMA3</li>
</ul>
</li>
 <li>Memory capacity &amp; performance features:
<ul>
 <li>Six-channel memory controller on each CPU</li>
 <li>Support for DDR4 memory speeds up to 2933MHz (up from 2666MHz)</li>
 <li>Single DIMM per channel operates at up to 2933MHz; two DIMMs per channel operate at up to 2666MHz</li>
 <li>Large-memory capabilities with Intel Optane DC Persistent Memory</li>
 <li>All CPU models support up to 1TB-per-socket system memory</li>
 <li>Optional CPU support for 2TB- or 4.5TB-per-socket system memory (only available on certain SKUs)</li>
</ul>
</li>
 <li>Introduction of Intel Speed Select processor models:
<ul>
 <li>Certain processors support three distinct operating points</li>
 <li>Each operating point provides a different number of CPU cores</li>
 <li>CPU clock and Turbo Boost speeds optimized for each core count</li>
</ul>
</li>
 <li>Integrated hardware-based security mitigations against side-channel attacks</li>
 <li>Fast links between CPU sockets with up to three 10.4GT/s UPI links</li>
 <li>I/O connectivity of 48 lanes of generation 3.0 PCI-Express per CPU</li>
 <li>CPU cores are arranged in an "Uncore" mesh interconnect</li>
 <li>Optimized Turbo Boost profiles allow higher frequencies even when many CPU cores are in use</li>
 <li>Direct PCI-Express (generation 3.0) connections between each CPU and peripheral devices such as network adapters, GPUs and coprocessors (48 PCI-E lanes per socket)</li>
 <li>Turbo Boost technology improves performance under peak loads by increasing processor clock speeds. Clock speeds are boosted higher even when many cores are in use. There are three tiers of Turbo Boost clock speeds depending upon the type of instructions being executed:
<ul>
	<li>Non-AVX: Operations that are not math intensive, or "light" AVX/AVX2 instructions which don't involve multiply/FMA</li>
	<li>AVX: Operations that heavily use the AVX/AVX2 units, or that use the AVX-512 unit (but not the multiply/FMA instructions)</li>
	<li>AVX-512: Operations that heavily use the AVX-512 units, including multiply/FMA instructions</li>
</ul>
</li>
 <li>Intel QuickData Technology (CBDMA) doubles memory-to-memory copy performance and supports MMIO memory copy</li>
 <li>Intel Volume Management Device (VMD) provides CPU-level device aggregation for NVMe SSD storage devices</li>
 <li>Intel Virtual RAID on CPU (VROC) provides RAID support for NVMe SSD storage devices</li>
 <li>Intel C620-series PCH chipset (formerly codenamed "Lewisburg") with improved connectivity:
<ul>
 <li>Up to four Intel X722 10GbE/1GbE Ethernet ports with iWARP RDMA support</li>
 <li>PCI-Express generation 3.0 x4 connection from the PCH to the CPUs</li>
 <li>Support for more integrated SATA3 6Gbps ports (up to 14)</li>
 <li>Support for more integrated USB 3.0 ports (up to 10)</li>
 <li>Integrated Intel QuickAssist Technology, which accelerates many cryptographic and compression/decompression workloads</li>
</ul>
</li>
 <li>Enhanced CPU Core Microarchitecture:
<ul>
 <li>Larger and improved branch predictor, higher throughput decoder, larger out-of-order window</li>
 <li>Improved scheduler and execution engine; improved throughput and latency of divide/sqrt</li>
 <li>More load/store bandwidth, deeper load/store buffers, improved prefetcher</li>
 <li>One or Two AVX-512 512-bit FMA units per core</li>
 <li>Support for the following AVX-512 instruction types: AVX512-F, AVX512-VL, AVX512-BW, AVX512-DQ, AVX512-CD</li>
 <li>1MB dedicated L2 cache per core</li>
 <li>A 10% (geomean) improvement in instructions per cycle (IPC) versus the "Broadwell" generation CPUs</li>
</ul>
</li>
 <li>Re-architected L2/L3 cache hierarchy:
<ul>
 <li>Each CPU core contains 1MB L2 private cache (up from 256KB)</li>
 <li>Each core's private L2 acts as primary cache</li>
 <li>Each CPU contains &gt;1.3MB/core of shared L3 cache (for when the private L2 cache is exhausted)</li>
 <li>The shared L3 cache is non-inclusive (does not keep copies of the L2 caches)</li>
 <li>Larger 64-entry L2 TLB for 1GB pages (up from 16 entries)</li>
</ul>
</li>
 <li>Dual or Triple Ultra Path Interconnect (UPI) links between processor sockets improve communication speeds for data-intensive applications</li>
 <li>RDSEED instruction for high-quality, non-deterministic, random seed values</li>
 <li>Hyper-Threading technology allows two threads to "share" a processor core for improved resource usage. Although useful for some workloads, it is frequently disabled for HPC applications.</li>
 <li>Hardware Controlled Power Management for more rapid and efficient decisions on optimal P- and C-State operating point</li>
</ul>

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