Xeon Phi

HPC with Intel Xeon Phi Coprocessors and the MIC Architecture

Microway manufactures customized clusters, servers, and WhisperStations that take advantage of Intel Xeon Phi Coprocessors and Intel’s software development tools.

The Xeon Phi is the first x86-based accelerator for heterogeneous HPC environments. Based upon the Many Integrated Core architecture (MIC), Xeon Phi is used to scale out traditional HPC systems. Phi offers a great balance of ease of use, performance, energy efficiency and cost in a solution optimized for highly-parallel HPC workloads.

Phi coprocessors provide more efficient performance than traditional CPUs. They include many more and smaller cores, many more threads, and wider vector units well-suited to highly parallel workloads. Features of interest include:

x86 Ring Architecture with up to 61 cores

  • Simple 64-bit execution environment or new 512-bit vector processing unit (Xeon Phi instruction set) available on each core

Over 1.2 TFLOPS double-precision floating point performance

  • Up to 4X the performance per watt of Xeon E5 family CPUs

Up to 16GB high-speed GDDR5 memory with ECC

  • Up to 352 GB/sec memory bandwidth

Intel Parallel Studio XE

Familiar x86 programming environment with Fortran, C/C++, and MPI based tools

  • Intel Math Kernel Library (MKL) support with automatic offload
  • Intel Parallel Studio XE supports developing and optimizing code for Xeon Phi Coprocessors explicitly
  • Intel Cluster Studio XE with Intel MPI Library supports development for parallel clusters with Xeon Phi
  • Portland Group (PGI) Accelerator compilers
  • 3rd-party cluster software products: MPICH, Bright Cluster Manager, PBS Professional, MOAB, Univa Grid Engine

Flexible execution and usage scenarios; runs its own native Linux OS

  • Hosted Offload/Heterogeneous Offload: support for running serial and moderately parallel codes on the Xeon CPU and offloading massively parallel workloads to the Xeon Phi coprocessor
  • Native Execution: transparently runs your basic but highly-parallel x86 code exclusively on Xeon Phi (requires the least amount of code changes)
  • Independent node/Symmetric mode: each Xeon Phi appears as an independent and IP addressable node for MPI applications and threads (allows easiest MPI programming)
  • Reverse Offload mode: run highly-parallel primary workloads natively on Xeon Phi and leverage occasional serial offload (Xeon CPU)

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Xeon Phi coprocessor for compute-bound workloads

Integrated in Microway WhisperStations, NumberSmasher Phi Servers and Phi Clusters

Specifications
Xeon Phi 3120A coprocessor

  • (57) 1.1GHz x86 processor cores
  • 1.003 TFLOPS double-precision performance
  • 6GB GDDR5 memory (5.0 GT/s)
  • 240 GB/s peak memory bandwidth
  • PCI-E x16 Gen2 interface to system
  • Heatsink with active cooling fan (300W TDP)
  • Passive version for Phi-optimized servers (300W TDP)

High-Density Xeon Phi coprocessor for memory-bound and capacity-bound workloads

Integrated in Microway NumberSmasher Phi Servers and NumberSmasher Phi Clusters

Specifications
Xeon Phi 5110P coprocessor

  • (60) 1.053GHz x86 processor cores
  • 1.011 TFLOPS double-precision performance
  • 8GB GDDR5 memory (5.0 GT/s)
  • 320 GB/s peak memory bandwidth
  • PCI-E x16 Gen2 interface to system
  • Passive Heatsink for Phi-optimized servers (225W TDP)

Highest-Performance, Large-Memory Xeon Phi coprocessor

Integrated in Microway NumberSmasher Phi Servers and NumberSmasher Phi Clusters

Specifications
Xeon Phi 5110P coprocessor

  • (61) 1.238GHz x86 processor cores
  • 1.208 TFLOPS double-precision performance
  • 16GB GDDR5 memory (5.5 GT/s)
  • 352 GB/s peak memory bandwidth
  • Turbo Boost up to 1.333GHz
  • PCI-E x16 Gen2 interface to system
  • Passive Heatsink for Phi-optimized servers (300W TDP)

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